View LTC2123-15_9077337.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 for more information www.linear.com/ltc2123 typical application features description dual 14-bit 250msps adc with jesd204b serial outputs the lt c ? 2123 is a 2- channel simultaneous sampling 250msps 14- bit a/d converter with serial jesd204b outputs. it is designed for digitizing high frequency, wide dynamic range signals. it is perfect for demanding communications applications with ac performance that includes 70 dbfs snr and 90 dbfs spurious free dynamic range ( sfdr). the 1.25 ghz input bandwidth allows the adc to under-sample high frequencies. the 5 gbps jesd204b serial interface simplifies the pcb design by minimizing the number of data lines required. the devclk + and devclk C inputs can be driven differ- entially with sine wave, pecl, or lvds signals. an optional clock divide-by-two circuit or clock duty cycle stabilizer maintains high performance at full speed for a wide range of clock duty cycles. 64k point 2-tone fft , f in = 71.1mhz and 69mhz, C7dbfs, 250msps applications n 5gbps jesd204b interface n 70dbfs snr n 90dbfs sfdr n low power: 864mw total n single 1.8v supply n easy to drive 1.5v p-p input range n 1.25ghz full power bandwidth s/h n optional clock divide by tw o n optional clock duty cycle stabilizer n low power sleep and nap modes n serial spi port for configuration n 48-lead (7mm 7mm) qfn package n communications n cellular base stations n software defined radios n medical imaging n high definition video n test and measurement instrumentation l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. serializer jesd204b logic analog input clock (250mhz or 500mhz) 14-bit adc ltc2123 jesd204b fpga or asic 50 50 ov dd 1.2v to 1.9v 5gbps serializer pll clock 2 or 1 jesd204b logic analog input 14-bit adc 50 50 ov dd 1.2v to 1.9v 5gbps 2123 ta01a 2123 ta01b ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 0 40 60 20 80 100 120 frequency (mhz) ltc 2123 2123fb
2 for more information www.linear.com/ltc2123 the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) pin configuration absolute maximum ratings supply voltages v dd , ov dd ...................................................... 0.3 v to 2v analog input voltage a ina /b + , a ina /b C ....................... C0. 3 v to (v dd + 0.2 v) sense ( note 3) ............................ C0. 3 v to (v dd + 0.2 v) digital input voltage de vclk + , devclk C , sysref + , sysref C , syn c ~ + , sync ~ C ( note 3) ....... C0. 3 v to (v dd + 0.3 v) cs , sdi , sck ( note 4) .......................... C 0.3 v to 3.9 v sdo ( note 4) ............................................ C 0.3 v to 3.9 v digital output voltage .................. C 0.3 v to (v dd + 0.3 v) operating ambient temperature range ltc 2 123 c ................................................ 0 c to 70 c ltc 2 123 i ............................................. C40 c to 85 c storage temperature range .................. C 65 c to 150 c top view 49 gnd uk package 48-lead (7mm 7mm) plastic qfn 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 v dd gnd a ina + a ina ? sense v ref v cm gnd a inb ? a inb + gnd v dd 13 14 15 16 17 18 19 20 21 22 23 24 v dd gnd devclk ? devclk + gnd sysref + sysref ? gnd sync~ + sync~ ? v dd v dd 48 47 46 45 44 43 42 41 40 39 38 37 v dd gnd cs sck sdi sdo of + of ? gnd gnd v dd v dd ov dd ov dd cmlout_a1 + cmlout_a1 ? cmlout_a0 + cmlout_a0 ? cmlout_b0 + cmlout_b0 ? cmlout_b1 + cmlout_b1 ? ov dd ov dd t jmax = 150c, t ja = 28c/w exposed pad ( pin 49) is gnd, must be soldered to pcb order information converter characteristics parameter conditions min typ max units resolution (no missing codes) l 14 bits integral linearity error differential analog input (note 6) l C5.5 0.85 5.5 lsb differential linearity error differential analog input l C0.9 0.25 0.9 lsb offset error (note 7) l C13 5 13 mv gain error internal reference external reference l C4.0 1.5 1 2.2 % fs %fs offset drift 20 v/oc full-scale drift internal reference external reference 30 10 ppm /oc ppm/oc transition noise 1.82 lsb rms lead free finish tape and reel part marking* package description temperature range ltc2123cuk#pbf ltc2123cuk#trpbf ltc2123uk 48-lead (7mm u 7mm) plastic qfn 0c to 70c ltc2123iuk#pbf ltc2123iuk#trpbf ltc2123uk 48-lead (7mm u 7mm) plastic qfn C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container . consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ (notes 1, 2) ltc 2123 2123fb
3 for more information www.linear.com/ltc2123 analog input the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 1.7v < v dd < 1.9v l 1.5 v p-p v in(cm) analog input common mode (a in + + a in C )/2 differential analog input (note 8) l v cm C 20mv v cm v cm + 20mv v v sense external voltage reference applied to sense external reference mode l 1.2 1.250 1.3 v i in1 analog input leakage current 0 < a in + , a in C < v dd , no clock l C1 1 a i in2 sense input leakage current 1.23v < sense < 1.27v l C1 1 a t ap sample-and-hold acquisition delay time 1 ns t jitter sample-and-hold acquisition delay jitter 0.15 ps rms cmrr analog input common mode rejection ratio 75 db bwC3db full-power bandwidth 1250 mhz dynamic accuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units snr signal-to-noise ratio 15mhz input 70mhz input 140mhz input l 67.1 70 69.7 69 dbfs dbfs dbfs sfdr spurious free dynamic range 2nd or 3rd harmonic 15mhz input 70mhz input 140mhz input l 71 90 85 80 dbfs dbfs dbfs spurious free dynamic range 4th harmonic or higher 15mhz input 70mhz input 140mhz input l 81 98 95 85 dbfs dbfs dbfs s /(n+d) signal-to-noise plus distortion ratio 15mhz input 70mhz input 140mhz input l 66.3 69.9 69.4 68.8 dbfs dbfs dbfs crosstalk crosstalk between channels up to 250mhz input C90 db internal reference characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) parameter conditions min typ max units v cm output voltage i out = 0 0.435 ? v dd C 18mv 0.435 ? v dd 0.435 ? v dd + 18mv v v cm output temperature drift 37 ppm/c v cm output resistance C1ma < i out < 1ma 4 v ref output voltage i out = 0 1.225 1.250 1.275 v v ref output temperature drift 30 ppm/c v ref output resistance C400a < i out < 1ma 7 v ref line regulation 1.7v < v dd < 1.9v 0.6 mv/v ltc 2123 2123fb
4 for more information www.linear.com/ltc2123 power requirements the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units v dd analog supply voltage (note 9) l 1.7 1.8 1.9 v ov dd output supply voltage cml current = 16ma, directly terminated (note 8) cml current = 16ma, ac terminated l l 1.2 1.4 1.9 1.9 v v i vdd analog supply current l 480 520 ma i ovdd output supply current per lane cml current = 12ma l 11 12 13.8 ma p diss power dissipation v dd = 1.8v, excluding ov dd power l 864 936 mw p sleep sleep mode power 2 mw p nap nap mode power 468 mw symbol parameter conditions min typ max units clock inputs (devclk + , devclk C ) v id differential input voltage (note 8) l 0.2 v v icm common mode input voltage internally set externally set (note 8) l 1.1 1.2 1.5 v v r in input resistance (see figure 2) 10 k c in input capacitance 2 pf differential digital inputs (sync~ + , sync~ C , sysref + , sysref C ) v id differential input voltage (note 8) l 0.2 v v icm common mode input voltage internally set externally set (note 8) l 1.1 1.2 1.5 v v r in input resistance 6.7 k c in input capacitance 2 pf digital inputs ( cs, sdi, sck) v ih high level input voltage v dd = 1.8v l 1.3 v v il low level input voltage v dd = 1.8v l 0.6 v i in input current v in = 0v to 3.6v l C10 10 a c in input capacitance (note 8) 3 pf sdo output (open-drain output. requires 2k pull-up resistor if sdo is used) r ol logic low output resistance to gnd v dd = 1.8v, sdo = 0v 200 i oh logic high output leakage current sdo = 0v to 3.6v l C10 10 a c out output capacitance (note 8) 4 pf lvds outputs (of + , of C ) v od differential output voltage 100 differential load l 247 350 454 mv v os common mode output voltage l 1.125 1.25 1.375 v digital inputs and outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) ltc 2123 2123fb
5 for more information www.linear.com/ltc2123 digital inputs and outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units cml outputs v diff cml differential output voltage output current set to 10ma output current set to 12ma output current set to 14ma output current set to 16ma 500 600 700 800 mvppd mvppd mvppd mvppd v oh output high level directly-coupled 50 to ov dd directly-coupled 100 differential ac-coupled ov dd ov dd C?v diff ov dd C?v diff v v v v ol output low level directly-coupled 50 to ov dd directly-coupled 100 differential ac-coupled ov dd C?v diff ov dd C?v diff ov dd C?v diff v v v v ocm output common mode level directly-coupled 50 to ov dd directly-coupled 100 differential ac-coupled ov dd C?v diff ov dd C?v diff ov dd C?v diff v v v r out output resistance single-ended differential l 80 50 100 120 the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) timing characteristics symbol parameter conditions min typ max units f s , 1/t s sampling frequency (note 9) l 50 250 mhz t l 1 clk low time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 1.9 1.5 2 2 10 10 ns ns t h 1 clk high time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 1.9 1.5 2 2 10 10 ns ns t dck devclk period 2x_clk spi register = 0 2x_clk spi register = 1 l l 4 2 20 10 ns ns spi port timing (note 8) t sck sck period write mode readback mode c sdo = 20pf, r pullup = 2k l l 40 250 ns ns t css cs to sck set-up time l 5 ns t csh sck to cs hold time l 5 ns t ds sdi set-up time l 5 ns t dh sdi hold time l 5 ns t do sck falling to sdo valid readback mode c sdo = 20pf, r pullup = 2k l 125 ns jesd204b timing (note 8) t bit, ui high speed serial bit period 2 lane mode (1 lane per adc) 4 lane mode (2 lanes per adc) l l 200 400 1000 1000 ps ps t jit total jitter of cml outputs (p-p) > 3.125gbps per lane (ber = 1e-15, note 8) < = 3.125gbps per lane (ber = 1e-12, note 8) l l 0.3 0.35 ui ui ltc 2123 2123fb
6 for more information www.linear.com/ltc2123 timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units t su_syn sync~ to devclk set-up time (note 8) l 0.6 ns t h_syn devclk to sync~ hold time (note 8) l 0.6 ns t su_sys sysref to devclk set-up time (note 8) l 0.2 (t dck C 0.32) ns t h_sys devclk to sysref hold time (note 8) l 0.32 ns lat p2 pipeline latency, 2-lane mode (note 10) l 13.5 13.5 t s lat p4 pipeline latency, 4-lane mode (note 10) l 19.5 19.5 t s t ds delay from devclk to serial data out (note 8) l 0.6 t s lat sc2 latency from sync~ assertion to comma out, 2-lane mode ( note 10) l 10 10 t s lat sc4 latency from sync~ assertion to comma out, 4-lane mode ( note 10) l 20 20 t s lat sl2 latency from sync~ de-assertion to las out, 2-lane mode ( notes 10, 11) l 6 6 t s lat sl4 latency from sync~ de-assertion to las out, 4-lane mode ( notes 10, 11) l 12 12 t s lat of overflow latency (note 10) l 6 6 t s t d _of1x analog delay of of with 1x_clk (note 8) l 1.4 1.7 2.0 ns t d _of2x analog delay of of with 2x_clk (note 8) l 1.6 1.9 2.2 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd ( unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latch-up. note 5: v dd = 1.8v, f sample = 250mhz, differential devclk + /devclk C = 2v p-p sine wave, input range = 1.5v p-p with differential drive, unless otherwise noted. note 6: integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 7: offset error is the offset voltage measured from C0.5lsb when the output code flickers between 01 1111 1111 1111 and 10 0000 0000 0000. note 8: guaranteed by design, not subject to test. note 9: recommended operating conditions. note 10: when the 2x_clk spi register bit is set, the devclk frequency is 2x the sampling frequency. when the 2x_clk bit is not set, the devclk frequency is equal to the sampling frequency. latency is measured in units of sampling periods (t s ), where t s is the inverse of the sampling frequency. note 11: when in subclass 0, the lane alignment sequence (las) latency measurement begins at the start of the frame following the detection of sync~ de-assertion. when in subclasses 1 or 2 this las latency measurement begins at the start of the first multiframe following the detection of sync~ de-assertion. ltc 2123 2123fb
7 for more information www.linear.com/ltc2123 typical performance characteristics 64k point fft , f in = 15.1mhz, C1dbfs, 250msps 64k point fft , f in = 70.1mhz, C1dbfs, 250msps 64k point fft , f in = 141.1mhz, C1dbfs, 250msps 64k point fft , f in = 185.1mhz, C1dbfs, 250msps 64k point fft , f in = 223.1mhz, C1dbfs, 250msps 64k point fft , f in = 383.1mhz, C1dbfs, 250msps integral nonlinearity (inl) differential nonlinearity (dnl) ac grounded input histogram 2123 g01 ?2.0 ?1.5 ?1.0 ?0.5 0.0 0.5 1.0 1.5 2.0 inl error (lsb) 0 4096 8192 12288 16384 output code 2123 g02 ?1.00 ?0.75 ?0.50 ?0.25 0.00 0.25 0.50 0.75 1.00 dnl error (lsb) 0 4096 8192 12288 16384 output code output code 8227 0 count 25000 20000 15000 10000 5000 30000 8237 8242 8232 2123 g03 2123 g04 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 0 40 60 20 80 100 120 frequency (mhz) 2123 g05 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 0 40 60 20 80 100 120 frequency (mhz) 2123 g06 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 0 40 60 20 80 100 120 frequency (mhz) 2123 g07 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 0 40 60 20 80 100 120 frequency (mhz) 2123 g08 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 0 40 60 20 80 100 120 frequency (mhz) 2123 g09 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 0 40 60 20 80 100 120 frequency (mhz) ltc 2123 2123fb
8 for more information www.linear.com/ltc2123 typical performance characteristics sfdr vs input level, f in = 70mhz, 1.5v range, 250msps snr vs input level, f in = 70mhz, 1.5v range, 250msps sfdr vs input frequency, C1dbfs, 1.5v range, 250msps snr vs input frequency, C1dbfs, 1.5v range, 250msps i vdd vs sample rate, f in = 15mhz, C1dbfs 64k point fft , f in = 907.1mhz C1dbfs, 250msps 64k point fft , f in = 421.1mhz, C1dbfs, 250msps 64k point fft , f in = 567.1mhz, C1dbfs, 250msps 64 k point 2- tone fft , f in = 71.1mhz and 69mhz, C7dbfs, 250msps 2123 g10 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 0 40 60 20 80 100 120 frequency (mhz) 2123 g11 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 0 40 60 20 80 100 120 frequency (mhz) 2123 g12 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 0 40 60 20 80 100 120 frequency (mhz) 2123 g13 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 0 40 60 20 80 100 120 frequency (mhz) 2123 g14 0 20 10 40 30 60 50 80 70 100 90 110 120 sfdr (dbc and dbfs) ?80 ?60 ?50 ?70 ?40 ?30 ?20 ?10 0 input level (dbfs) dbfs dbc 2123 g15 0 20 10 40 30 60 50 70 80 snr (dbc and dbfs) ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 input level (dbfs) dbfs dbc 2123 g16 50 60 55 75 70 65 95 90 85 80 100 sfdr (dbfs) 0 200 400 600 800 1000 input frequency (mhz) 2123 g17 40 45 60 50 55 70 65 75 snr (dbfs) 0 200 400 600 800 1000 input frequency (mhz) 2123 g18 350 370 470 410 390 450 430 510 490 530 i vdd (ma) 40 80 120 200160 240 280 sample rate (msps) 4 lane 2 lane ltc 2123 2123fb
9 for more information www.linear.com/ltc2123 typical performance characteristics cmlout bathtub curve, 2.5gbps cmlout bathtub curve, 5gbps cmlout eye diagram, 5gbps, 8in (20cm) fr4 cmlout eye diagram, 2.5gbps cmlout eye diagram, 5gbps 2123 g19 1e-15 1e-09 1e-11 1e-13 1e-01 1e-03 1e-05 1e-07 bit error rate (ber) 0.0 0.4 0.2 0.6 0.8 1.0 unit interval (ui) 2123 g20 100mv/div 66.7ps/div 2123 g21 1e-15 1e-09 1e-11 1e-13 1e-01 1e-03 1e-05 1e-07 bit error rate (ber) 0.0 0.4 0.2 0.6 0.8 1.0 unit interval (ui) 2124 g22 100mv/div 33.3ps/div 2123 g23 100mv/div 33.3ps/div ltc 2123 2123fb
10 for more information www.linear.com/ltc2123 pin functions v dd ( pins 1, 12, 13, 23, 24, 37, 38, 48): 1.8 v power supply. bypass to ground with 0.1 f ceramic capacitors . adjacent pins can share bypass capacitor. gnd (pins 2, 8, 11, 14, 17, 20, 39, 40, 47, exposed pad pin 49): device power ground. the exposed pad must be soldered to the pcb ground. a ina + /a ina C (pins 3, 4): analog input pair for channel a. sense (pin 5): reference programming pin. connecting sense to v dd selects the internal reference and a 0.75v input range. an external reference between 1.2 v and 1.3v applied to sense selects an input range of 0.6 ? v sense . v ref (pin 6): reference voltage output. bypass to ground with a 2.2f ceramic capacitor. nominally 1.25v. v cm (pin 7): common mode bias output. nominally equal to 0.435 ? v dd . v cm should be used to bias the common mode of the analog inputs. bypass to ground with a 0.1 f ceramic capacitor. a inb C /a inb + (pins 9, 10): analog input pair for channel b. devclk C /devclk + (pins 15, 16): device clock input pair. the sample clock is derived from this clock signal. in divide-by-one mode, the analog signal is sampled on the falling edge of devclk (devclk = devclk + C devclk C ). devclk may optionally be divided by two. in subclass 1 a low to high transition of the sysref signal will initialize the divide-by-two circuit on the rising edge of devclk. in subclass 2 a low to high transition of the sync~ signal will initialize the divide-by-two circuit on the rising edge of devclk. sysref + /sysref C (pins 18, 19): a jesd204b subclass 1 input signal pair. a low to high transition of sysref is sampled on the rising edge of devclk to reset the inter - nal dividers and set up deterministic latency (sysref = sysref + C sysref C ). sync~ + /sync~ C (pins 21, 22): a jesd204b synchro- nization input signal pair. used to establish initial code group synchronization for all three subclasses. a low level of the sync~ signal causes the ltc2123 to output k28.5 commas (sync~ = sync~ + C sync~ C ). in subclass 2 a low to high transition of sync~ is sampled on the rising edge of devclk to reset the internal dividers and set up deterministic latency. ov dd (pins 25, 26, 35, 36): 1.2 v to 1.9 v output driver supply. bypass each pair to ground with 0.1 f ceramic capacitors. cmlout _b1 C / cmlout _b1 + ( pins 27, 28): current mode logic output pair for channel b lane 2. must be terminated with a 50 resistor to ov dd , a differential 100 resistor to the complementary output, or ac coupled to another termination voltage. cmlout _b0 C / cmlout _b0 + ( pins 29, 30): current mode logic output pair for channel b lane 1. must be terminated with a 50 resistor to ov dd , a differential 100 resistor to the complementary output, or ac coupled to another termination voltage. cmlout _a0 C / cmlout _a0 + ( pins 31, 32): current mode logic output pair for channel a lane 1. must be terminated with a 50 resistor to ov dd , a differential 100 resistor to the complementary output, or ac coupled to another termination voltage. cmlout _a1 C / cmlout _a1 + ( pins 33, 34): current mode logic output pair for channel a lane 2. must be terminated with a 50 resistor to ov dd , a differential 100 resistor to the complementary output, or ac coupled to another termination voltage. of C /of + (pins 41, 42): over/underflow lvds digital output. of is high when an overflow or underflow has occurred. the overflows for channel a and channel b are multiplexed together and transmitted at twice the sample frequency (of = of + C of C ). sdo (pin 43): serial interface data output. sdo is the optional serial interface data output. data on sdo is read back from the mode control registers and can be latched on the falling edge of sck. sdo is an open-drain n-channel mosfet output that requires an external 2 k pull-up resis- tor from 1.8 v to 3.3 v. if readback from the mode control registers is not needed, the pull-up resistor is not neces- sary and sdo can be left unconnected. ltc 2123 2123fb
11 for more information www.linear.com/ltc2123 block diagram pin functions sck sdi sdo sense v cm v ref spi control cs 2.5gbps serializer 2.5gbps serializer 2.5gbps/ 5gbps serializer 2.5gbps/ 5gbps serializer 8b/10b encoder alignment monitors sysref decode sync decode pll and clk dividers 1.25v reference adc a adc b clk rec sysref rec sync rec 8b/10b encoder alignment monitors 8b/10b encoder alignment monitors 8b/10b encoder alignment monitors cml driver cml driver cml driver cml driver 2123 bd01 analog input a analog input b devclk ch. a, lane 1, 2.5gbps, 2 lanes/adc ch. a, lane 0, 2.5gbps, 2 lanes/adc or ch. a, lane 0, 5gbps, 1 lane/adc ch. b, lane 2, 2.5gbps, 2 lanes/adc or ch. b, lane 1, 5gbps, 1 lane/adc ch. b, lane 3, 2.5gbps, 2 lanes/adc sysref sync~ test patterns data mapping data mapping lane align sequence lane align sequence lane align sequence lane align sequence scrambler 1+x 14 +x 15 scrambler 1+x 14 +x 15 scrambler 1+x 14 +x 15 scrambler 1+x 14 +x 15 figure 1. functional block diagram sdi (pin 44): serial interface data input. sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. sdi can be driven with 1.8v to 3.3v logic. sck (pin 45): serial interface clock input. sck is the serial interface clock input. sck can be driven with 1.8v to 3.3v logic. cs (pin 46): serial interface chip select input. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. cs can be driven with 1.8 v to 3.3 v logic. ltc 2123 2123fb
12 for more information www.linear.com/ltc2123 timing diagram n+1 n+13 n-14 n-13 n+14 analog input n devclk cmlout_a0 t ap lat p2 t bit t h t ds t l t conv cmlout_b0 n-1 n n-14 n-13 n-1 n 2123 td01 n ?1 devclk n+3 n+4 n?1 n+2 n+1 n n+19 n+20 n+18 n+21 n+22 analog input t ap t conv n?3 n?19 n?21 n?1 2123 td02 n?3 n?19 n?21 n?1 n?2 n?18 n?20 n n?2 n?18 n?20 n cmlout_a0 cmlout_b0 cmlout_a1 cmlout_b1 lat p4 t ds two -lane timing (one lane per adc), f devclk = f s four-lane timing ( tw o lane per adc), f devclk = f s note: devclk = devclk + C devclk C ltc 2123 2123fb
13 for more information www.linear.com/ltc2123 timing diagram over-flow (of) timing 2x_clk mode over flow (of) timing, 1x_clk mode n+1 n+5 n+6 analog input n devclk (1x_clk) t ap lat of t d_of1x n+7 of ch a n-7 ch a n-6 ch b n-6 ch a n-5 ch a n ch b n ch a n+1 2123 td03 ch b n+1 ch b n-7 n?1 n+1 n+5 n+6 analog input n devclk (2x_clk) t ap lat of t d_of2x n+7 of ch a n-7 ch a n-6 ch b n-6 ch a n-5 ch a n ch b n ch a n+1 2123 td04 ch b n+1 ch b n-7 n?1 ltc 2123 2123fb
14 for more information www.linear.com/ltc2123 timing diagram note: devclk = devclk + C devclk C , of = of + C of C , sysref = sysref + C sysref C , sync~ = sync~ + C sync~ C 2123 td05 devclk sysref t h_sys t su_sys 2123 td06 devclk sync~ t h_syn t su_syn sysref timing (subclass 1) sync~ rising edge clock reset timing (subclass 2) ltc 2123 2123fb
15 for more information www.linear.com/ltc2123 spi timing 2123 st01 t css t csh t sck sck sdi sdo high impedance x x x x a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 cs r/w t dh t ds 2123 st02 sck sdi sdo high impedance high impedance t do x x x x xxxxxxxx a6 a5 a4 a3 a2 a1 a0 cs rw d1 d0 d2d3d4d5d6d7 spi timing, write mode spi timing, read mode ltc 2123 2123fb
16 for more information www.linear.com/ltc2123 definitions adc performance terms aperture delay time the time it takes for the input signal to be held by the sample-and-hold circuit after the rising edge of devclk + is equal to the falling edge of devclk C on the sampling edge of devclk. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C20log (2 ? f in ? t jitter ) crosstalk crosstalk is the coupling from one channel ( being driven by a full-scale signal) onto the other channel ( being driven by a C1dbfs signal). intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion ( imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc . for example, the 3 rd order imd terms include (2fa + fb), (fa + 2fb), (2fa C fb) and (fa C 2 fb). the 3 rd order imd is defined as the ratio of the rms value of either input tone to the rms value of the largest 3rd order imd product. signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [ s/(n+d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band lim - ited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise ( snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components, except the first five harmonics. spurious free dynamic range (sfdr) the ratio of the rms input signal amplitude to the rms value of the peak spurious spectral component expressed in dbc. sfdr may also be calculated relative to full scale and expressed in dbfs. ltc 2123 2123fb
17 for more information www.linear.com/ltc2123 definitions serial interface terms 8b/10b encoding a data encoding standard that encodes an 8- bit octet into a 10- bit code-group ( ieee std 802.3-2002 part 3, clause 36.2). the resulting code- group is ideal for serial transmis - sion for two fundamental reasons: 1) the receiver does not require a high speed clock to capture the data because the code-groups are run-length limited to ensure a sufficient number of transitions for pll-based clock recovery 2) ac coupling is permitted because the code-groups are dc balanced (see running disparity). a table of the 256 possible input octets with the resulting 10-bit code- groups is documented in ieee std 802.3-2002 part 3 table 36-1. a name associated with each of the 256 data code-groups is formatted dx.y, with x ranging from 0 to 31 and y ranging from 0 to 7. additionally, table 36-2 of the standard defines a set of 12 special code-groups used as non-data characters (such as commas) with the naming format of kx.y. current mode logic (cml) a circuit technique used to implement differential high speed logic. cml employs differential pairs ( usually n- type) to steer current into resistive loads. it is possible to implement any logic function using cml. the output swing and offset is dependent on the bias current, the load resistance, and termination resistance. this product family uses cml drivers to transmit high speed serial data to the outside world. the output driver bias current is programmable from 10 ma to 16 ma, generating a signal swing of approximately 250mv p-p (500 mvppd) to 400mv p-p (800 mvppd) across the combined internal and external termination resistance of 25 (50 source//50 termination) on each output ( mvppd stands for mv p-p differential). code-group the 10- bit output from an 8 b/10b encoder or the 10-bit input to the 8b/10b decoder. comma a special 8 b/10b code-group containing the binary se- quence 0011111 or 1100000. commas are used for frame alignment and synchronization because a comma sequence cannot be generated by any combination of normal code-groups ( unless a bit error occurs). there are three special code-groups that contain a comma, k28.1, k28.5, and k28.7. for brevity, each of these three special code-groups are often called a comma, but in the strictest sense it is the first 7 bits of these code-groups that are designated a comma . dc balanced signal a specially conditioned signal that may be ac coupled with minimal degradation to the signal. dc balance is achieved when the average number of 1 s and 0 s are equal, elimi- nating the undesirable effects of dc wander on the receive side of the coupling capacitor. when 8 b/10b coding is used, dc balance is achieved by following disparity rules (see running disparity). de-scrambler a logic block that restores scrambled data to its pre- scrambled state . a self aligning de-scrambler is based on the same pseudo random bit sequence as the scrambler, so it requires no alignment signals . in this product fam - ily the scrambler is based on the 1+x 14 +x 15 polynomial, and the self aligning process results in an initial loss of 15 bits, or one adc sample. deterministic latency a predictable and repeatable delay from the input to the output of the system . jesd204b subclasses 1 and 2 em- ploy technologies that support a predictable and repeatable pipeline delay through the system. frame the ltc2123 frame consists of two complete code- groups per lane, and constitutes one complete adc sample per lane. ltc 2123 2123fb
18 for more information www.linear.com/ltc2123 frame alignment monitoring ( fam ) after initial frame synchronization has been established, frame alignment monitoring enables the receiver to verify that code-group alignment is maintained without the loss of data. this is done by substituting a k28.7 comma for the last code-group of the frame when certain conditions are met. the receiver uses this comma as a position marker within the frame for alignment verification. after decoding the data, the receiver replaces the k28.7 comma with the original data. initial frame synchronization the process of communicating frame boundary informa - tion to the receiver for alignment purposes . the receiver asserts the sync~ signal, causing the adc to transmit k28.5 commas to the receiver. the receiver de-asserts the sync~ signal, and the adc ceases transmission of com - mas according to the rules of the particular sub-class and mode of operation. the point of termination of commas in the data stream marks the frame boundary. lane alignment monitoring (lam) in jesd204b, lane alignment is attained and monitored through the use of the 8 b/10b k28.3 special characters. these characters are conditionally embedded in the data stream at the end of the multiframe. the receiver uses this character as a position marker within the multiframe for lane alignment verification. after decoding the data, the receiver replaces the k 28.3 character with the original data. local multiframe clock (lmfc) an internal clock within each device of a jesd204b system that marks the multiframe boundary. multiframe a group of frames intended to be of long duration com- pared to lane mismatches in multiple lane systems. in jesd204b the maximum multiframe length is 32 frames. there is no external multiframe clock in a jesd204b sys - tem, so the signal marking the multiframe boundaries is referred to as the local multiframe clock (lmfc). definitions octet the 8- bit input to an 8 b/10b encoder, or the 8- bit output from an 8b/10b decoder. run-length limited (rll) data that has been encoded for the purpose of limiting the number of consecutive 1s or 0s in a data stream. this process guarantees that there will be an adequate number of transitions in the serial data for the receiver to lock onto with a phase-locked loop and recover the high speed clock. running disparity in order to maintain dc balance most 8 b/10b code-groups have two output possibilities for each input octet. the run - ning disparity is calculated to determine which of the two code - groups should be transmitted to maintain dc balance. the disparity of a code-group is analyzed in two segments called sub-blocks. sub-block1 consists of the first six bits of a code-group and sub-block2 consists of the last four bits of a code-group. when a sub-block is more heavily weighted with 1 s the running disparity is positive, and when it is more heavily weighted with 0 s the running disparity is negative. when the number of 1s and 0s are equal in a sub-block, the running disparity remains unchanged. the polarity of the current running disparity determines which code-group should be transmitted to maintain dc balance. for a complete description of disparity rules, refer to ieee std 802.3-2002 part 3, clause 36.2.4.4. pseudo random bit sequence (prbs) a data sequence having a random nature over a finite inter - val. the most commonly used prbs test patterns may be described by a polynomial in the form of 1+x m +x n and have a random nature for the length of up to 2 n-1 bits, where n indicates the order of the prbs polynomial and m plays a role in maximizing the length of the random sequence. scrambler a logic block that applies a pseudo random bit sequence to the input octets to minimize the tonal content of the high speed serial bit stream. ltc 2123 2123fb
19 for more information www.linear.com/ltc2123 converter operation the ltc2123 is a two-channel , 14-bit 250 msps a/d converter with jesd204b high speed serial outputs. the analog inputs must be driven differentially. the devclk inputs should be driven differentially for optimal perfor - mance. the high speed serial interface is capable of data rates of up to 5 gbps per lane. the overflow/underflow indicators are available as part of the high speed serial data, and optionally as low-latency double data rate lvds outputs. a spi port provides programmability of multiple user options. analog input the analog inputs are differential cmos sample- and hold circuits ( figure 2). the inputs must be driven differentially around a common mode voltage set by the v cm output pin, which is nominally 0.8v . for the 1.5 v input range, the inputs should swing from v cm C 0.375 v to v cm + 0.375 v. there should be 180 phase difference between the inputs. the two channels are simultaneously sampled by a shared clock circuit. applications information input drive circuits input filtering if possible, there should be an rc lowpass filter right at the analog inputs. this lowpass filter isolates the drive circuitry from the a/d sample- and- hold switching, and also limits wide band noise from the drive cir cuitry. figure 3 shows an example of an input rc filter. the rc compo- nent values should be chosen based on the applications specific input frequency. t ransformer-coupled circuits figure 3 shows the analog input being driven by an rf transformer with the common mode supplied through a pair of resistors via the v cm pin. at higher input frequencies a transmission line balun transformer (figures 4 and 5) has better balance, resulting in lower a/d distortion. figure 2. equivalent input circuit for a single channel 2pf r on 20 r on 20 v dd v dd ltc2123 a in + 2123 f02 2pf v dd a in ? devclk ? devclk + 2pf 2pf 1.2v 10k 10k 1 or 2 figure 3. analog input circuit using a transformer. recommended for input frequencies from 5mhz to 70mhz figure 4. recommended front-end circuit for input frequencies from 15mhz to 150mhz 25 25 4.7 4.7 10 0.1f 10pf 0.1f ltc2123 in 0.1f t1: macom etc1-1t 2123 f03 a in + a in ? v cm 45 45 10 4.7 4.7 0.1f 0.1f 100 in 0.1f 0.1f t1: maba 007159-000000 t2: wbc1-1l 2123 f04 ltc2123 a in + a in ? v cm ltc 2123 2123fb
20 for more information www.linear.com/ltc2123 amplifier circuits figure 6 shows the analog input being driven by a high speed differential amplifier. the output of the amplifier is ac coupled to the a/d so the amplifiers output common mode voltage can be optimally set to minimize distortion. at very high frequencies an rf gain block will often have lower distortion than a differential amplifier. if the gain block is single-ended, then a transformer circuit (figures 3 through 5) should convert the signal to differential before driving the a/d. the a/d cannot be driven single-ended. reference the ltc2123 has an internal 1.25 v voltage reference. for a 1.5 v input range with internal reference, connect sense to v dd . for a 1.5 v input range with an external reference, apply a 1.25v reference voltage to sense (figure 7). device clock (devclk) input the devclk is used to derive the adc sample clock, so the signal quality of the devclk inputs strongly affects the a/d noise performance. the devclk inputs should be treated as analog signals. do not route them next to digital traces on the circuit board. the devclk inputs are internally biased to 1.2 v through 10 k equivalent resistance (figure 8). figure 5. recommended front-end circuit for input frequencies from 150mhz to 900mhz figure 6. front-end circuit using a high speed differential amplifier figure 7. reference circuit figure 8. equivalent devclk input circuit applications information 45 45 10 100 4.7 4.7 0.1f 0.1f in 0.1f 0.1f t1: maba 007159-000000 2123 f05 ltc2123 a in + a in ? v cm 4.7 4.7 50 50 0.1f a in + a in ? 0.1f 3pf 3pf 3pf v cm ltc2123 2123 f06 input 0.1f scaler/ buffer v ref 2.2f sense 1.25v ltc2123 2123 f07 5 adc reference sense detector v dd ltc2123 2123 f08 1.2v 10k 10k devclk + devclk ? ltc 2123 2123fb
21 for more information www.linear.com/ltc2123 applications information if the common mode of the driver is within 1.1 v to 1.5 v, it is possible to drive the devclk inputs directly. otherwise a transformer or coupling capacitors are needed (figures 9 and 10). the maximum ( peak) voltage of the input signal should never exceed v dd +0.1v or go below C0.1v. the adc sample clock is derived from devclk. for good performance the sample clock should have a 50% (5%) duty cycle. there are two programmable options provided in the ltc2123 that will ensure a 50% duty cycle sample clock: 1) an optional devclk divide-by-two circuit is provided in the clock path to convert a 2 x harmonic devclk to a 50% duty cycle sample clock. the 2 x_clk option is enabled via spi register 2, bit 2. 2) if a 2 x clock is not available, the clock duty cycle stabilizer ( dcs) circuit may be enabled. when enabled, the devclk duty cycle can vary from 30% to 70% and the duty cycle stabilizer will maintain a constant 50% internal duty cycle. the duty cycle stabilizer is enabled via spi register 2, bit 0. if the 2 x_clk option is selected in the spi register the duty cycle stabilizer is disabled regardless of the state of the dcs_en bit. for applications where the sample rate needs to be changed quickly and a 2 x clock is not available, both the 2x_clk and the clock duty cycle stabilizer may be disabled. in this case, care should be taken to make the devclk a 50% (5%) duty cycle. overflow detection an overflow ( of) is detected when the analog inputs are either over-ranged or under-ranged. there are two mechanisms for reporting an of event: 1) the of bit is transmitted as part of the serial bit stream following the lsb of the adc data. 2) there is a separate lvds output pair dedicated to early indication of an of event . the lvds of indicator has a latency of 6 sample clock cycles. both adc of signals are multiplexed to one output pair at double data rate . the channel a of signal is active on the first half of the internal sample clock and the channel b of signal is active on the second half of the cycle. the lvds of indicator is output at standard lvds levels: 3.5ma output current and a 1.25 v output common mode voltage. an external 100 differential termination resistor is required to function properly. the termination resis - tor should be located as close as possible to the lvds receiver. if used, this lvds output pair is enabled via spi register 2, bit 1. d ata format table 1 shows the relationship between the analog input voltage, the digital data output bits and the overflow bit. the output data format is offset binary. figure 9. sinusoidal devclk drive ltc2123 v dd 2123 f09 1.2v 10k 10k 50 100 50 0.1f 0.1f 0.1f t1: macom etc1-1-13 ltc 2123 2123fb
22 for more information www.linear.com/ltc2123 applications information figure 10. ac coupled devclk drive v dd ltc2123 pecl or lvds input 2123 f10 1.2v 10k 10k 100 0.1f 0.1f devclk + devclk ? power down modes the power down modes are controlled through register 1 of the spi interface. the two adc channels may be powered down separately, simultaneously, or the entire device may be placed in sleep mode to conserve power. the pda and pdb spi register bits are used to power down each adc channel individually while keeping the internal clock and reference circuits active . sleep powers down the entire device, resulting in < 5 mw power consumption. the amount of time required to recover from sleep mode depends on the size of the bypass capacitor on v ref . for the suggested value of 2.2 f, the a/d will stabilize after 0.1ms + 2500 ? tp where tp is the period of the sampling clock. nap mode in "nap mode both adc cores are powered down while the internal clock circuits, reference circuits, and serial table 1. output codes vs input voltage a in + C a in C (1.5v range) of d13-d0 (offset binary) >0.75v +0.75v +0.749908v 1 0 0 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 +0.0000915 v +0.000000v C0.0000915v C0.0001831v 0 0 0 0 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 C0.7499084 v C0.75v < C0.75v 0 0 1 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000 interface stay active, allowing faster wake-up. while in nap mode the data at the output of the each adc is forced to zero. the spi and the serial test patterns are fully func - tional in nap mode, so any test pattern may be selected through the spi. recovering from nap mode requires at least 100 clock cycles. jesd204b overview jesd204b is a jedec standard that defines a high speed serial interface for data converters. the advantages of serialization include the simplification of printed circuit board ( pcb) layout through the reduction of traces on the pcb. jesd204b solves several problems associated with serial data transmission, such as the identification of the start of a sample and the proper alignment of data arriving on multiple lanes. jesd204 b devices encode the parallel data using industry standard 8 b /10 b code- groups ( ieee 802.3-2002, section 3). there is an overhead requirement of 2 bits for every 8 encoded bits (8 bits are encoded to 10 bits), but encoding the adc data prior to serialization provides certain benefits which make the transmitted data more suitable for serial transmission: these benefits include dc balance (for ac coupling), and run- length limiting ( providing a sufficient number of transitions for the receiver to extract the clock from the data with a phase-locked loop). figures 11 and 12 illustrate the transformation of adc sampled data into 10-bit code groups prior to transmission. the code-groups are formed into frames and multiframes . for the ltc2123, there are two possible lane configurations: 1) tw o lane mode ( one lane per adc) operating at up to 5gbps per lane. 2) four lane mode ( two lanes per adc) operating up to 2.5gbps per lane. sync~ signal in addition to the high speed serial lanes, jesd204b requires the use of a sync ~ ( active low) signal. the sync~ signal originates from the receiver and serves as a request to the ltc2123 that synchronization is required (jesd204b 4.9). ltc 2123 2123fb
23 for more information www.linear.com/ltc2123 applications information adc channel a output word formation msb channel a, octet 0 channel a, octet 1 channel a, final octet 0 channel a, final octet 1 octet mapping one frame bit 0 of code group 0 is transmitted first serial out for channel a (lane 0) channel a, 8b/10b code group 0 (most significant word) channel a, 8b/10b code group 1 (least significant word) lsb bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 2 bit 1 bit 0 c d e a b i f g h j bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 2 bit 1 bit 0 c d e a b i f g h j bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 of bit ? jesd204b processing (scrambling, substitutions, etc.) 8b/10b encoder jesd204b processing (scrambling, substitutions, etc.) 8b/10b encoder adc channel b output word formation msb channel b, octet 0 channel b, octet 1 channel b, final octet 0 channel b, final octet 1 octet mapping one frame 2123 f11 bit 0 of code group 0 is transmitted first serial out for channel b (lane 1) channel b, 8b/10b code group 0 (most significant word) channel b, 8b/10b code group 1 (least significant word) lsb bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 2 bit 1 bit 0 c d e a b i f g h j bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 2 bit 1 bit 0 c d e a b i f g h j bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 of bit ? figure 11. word formation of each lane in two -lane mode ltc 2123 2123fb
24 for more information www.linear.com/ltc2123 applications information figure 12. word formation of each lane in four-lane mode adc channel a output word formation, even samples msb channel a, octet 0, even sample channel a, octet 1, even sample channel a, final octet 0, even sample channel a, final octet 1, even sample octet mapping octet mapping one frame bit 0 of code group 0 is transmitted first serial out for channel a even samples (lane 0) channel a, 8b/10b code group 0, even sample (most significant word) channel a, 8b/10b code group 1, even sample (least significant word) lsb bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 2 bit 1 bit 0 c d e a b i f g h j bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 2 bit 1 bit 0 c d e a b i f g h j bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 of bit ? jesd204b processing (scrambling, substitutions, etc.) 8b/10b encoder jesd204b processing (scrambling, substitutions, etc.) 8b/10b encoder adc channel b output word formation, even samples msb channel b, octet 0, even sample channel b, octet 1, even sample channel b, final octet 0, even sample channel b, final octet 1, even sample one frame bit 0 of code group 0 is transmitted first serial out for channel b even samples (lane 2) channel b, 8b/10b code group 0, even sample (most significant word) channel b, 8b/10b code group 1, even sample (least significant word) lsb bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 2 bit 1 bit 0 c d e a b i f g h j bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 2 bit 1 bit 0 c d e a b i f g h j bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 of bit ? adc channel a output word formation, odd samples msb channel a, octet 0, odd sample channel a, octet 1, odd sample channel a, final octet 0, odd sample channel a, final octet 1, odd sample one frame bit 0 of code group 0 is transmitted first serial out for channel a odd samples (lane 1) channel a, 8b/10b code group 0, odd sample (most significant word) channel a, 8b/10b code group 1, odd sample (least significant word) lsb bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 2 bit 1 bit 0 c d e a b i f g h j bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 2 bit 1 bit 0 c d e a b i f g h j bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 of bit ? adc channel b output word formation, odd samples msb channel b, octet 0, odd sample channel b, octet 1, odd sample channel b, final octet 0, odd sample channel b, final octet 1, odd sample one frame 2123 f12 bit 0 of code group 0 is transmitted first serial out for channel b odd samples (lane 3) channel b, 8b/10b code group 0, odd sample (most significant word) channel b, 8b/10b code group 1, odd sample (least significant word) lsb bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 h g f e d c b a bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 2 bit 1 bit 0 c d e a b i f g h j bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 2 bit 1 bit 0 c d e a b i f g h j bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 of bit ? ltc 2123 2123fb
25 for more information www.linear.com/ltc2123 applications information jesd204b link configuration parameters there are 20 link configuration parameters used by jesd204b to describe the operation of the link (jesd204b 8.3, table 20). the receiver must match the parameters of the ltc2123 in order for error free communication to take place. table 2 summarizes the link parameters of the ltc2123. jesd204b subclasses there are 3 subclasses of operation for jesd204b. these subclasses provide different levels of deterministic latency through the communication link. below is a simple overview of the three subclasses: subclass 0: no deterministic latency support is provided. there is no support for resetting and aligning critical clocks between the ltc2123 and the receiver. the ltc2123 is compliant with this subclass. subclass 1: deterministic latency is obtained through the addition of a sysref signal. the sysref signal provides precise timing information for aligning critical clocks in the ltc2123 and in the receiver. the low to high transition of sysref is sampled by the rising edge of devclk, so the devclk and sysref signals should originate from close proximity to each other and delays between these signals should closely match (figure 13). the ltc2123 is compliant with this subclass. table 2. jesd204b link configuration parameters jesd204b link configuration parameter ltc2123 device value for one lane per adc mode ltc2123 device value for two lane per adc mode encoding did<7:0> spi programmable spi programmable binary value adjcnt<3:0> na, 0000 na, 0000 binary value bid<3:0> spi programmable spi programmable binary value adjdir na, 0 na, 0 binary value phadj na, 0 na, 0 binary value lid C1 <4:0> cmlout_a0 cmlout_a1 cmlout_b0 cmlout_b1 0_0000 na 0_0001 na 0_0000 0_0001 0_0010 0_0011 binar y value minus 1 scr<0> spi programmable binar y value l C1 <4:0> 0_0001 0_0011 binary value minus 1 f C1 <7:0> 0000_0001 0000_0001 binary value minus 1 k C1 <4:0> spi programmable spi programmable binary value minus 1 m C1 <7:0> 0000_0001 0000_0001 binary value minus 1 cs<1:0> 01 01 binary value n C1 <4:0> 0_1101 0_1101 binary value minus 1 subclassv<2:0> spi programmable spi programmable binary value n C1 <4:0> 0_1111 0_1111 binary value minus 1 jesdv<2:0> 001 001 binary value s C1 <4:0> 0_0000 0_0001 binary value minus 1 hd 0 0 binary value cf<4:0> 0_0000 0_0000 binary value fchk<7:0> sum of all fields mod 256 sum of all fields mod 256 binary value ltc 2123 2123fb
26 for more information www.linear.com/ltc2123 applications information figure 13. jesd204b subclass 1 configuration note: internal clocks are reset by sysref on the rising edge of the device clock. for deterministic latency, each sysref/device clock pair should have matched delays, and should satisfy setup and hold requirements, t su_syn and t h_sys . ltc2123 ltc2123 5gbps lane 5gbps lane matched delays matched delays matched delays sysref 3 device clock 3 device clock 1 sysref 1 sysref 2 device clock 2 5gbps lane 5gbps lane sync~ fpga or jesd204b asic clk gen 2123 f11 as an added subclass 1 protection, the ltc2123 pro- vides an optional alert mode. depending on the sysref generation circuit, there could be an erroneous or short pulse generated as the first sysref pulse. to avoid the possibility of alignment errors due to a compromised first pulse, an optional alert mode may be enabled in the spi . while in alert mode, the ltc2123 will ignore the first sysref pulse, and reset critical clocks with the second pulse. the first pulse, therefore, serves to arm the system, and the second pulse resets the clocks. after a program - mable number of multiframes without a second sysref pulse, the system is disarmed until the next sysref pulse is received. figure 14 illustrates the state machine of the subclass 1 alert mode. subclass 2: deterministic latency support is obtained by sampling the low to high transition of the sync~ signal with the rising edge of devclk. upon detection of the sync~ low to high transition, the critical clocks are re- aligned. the ltc2123 is compatible with this subclass, but the detection resolution is always determined by the adc devclk frequency. ltc 2123 2123fb
27 for more information www.linear.com/ltc2123 applications information reset sample sysref sysref received wait count multiframes; sample sysref; no sysref received align 2123 f13 sysref received and multiframe count r no sysref received multiframe count > r multiframe count r multiframe count > r alert align multiframe boundry to sysref; count multiframes; sample sysref; reset count when sysref received; figure 14. alert mode of subclass 1 code-group synchronization (jesd204b 5.3.3.1) in order for each receiver to properly align to the received serial data, each adc transmitter must communicate the location of the start of a code-group and the start of a frame to its receiver. when multiple adc devices are transmitting on multiple lanes, this alignment must take place on all lanes simultaneously in order for the receivers to determine the relationship between lanes. a receiver initiates synchronization by asserting its sync~ signal . when multiple receivers are present, the sync~ signals of all receivers may be logically ored to provide synchro - nization requests to all adc devices simultaneously . the following synchronization process may be initiated by the receivers at any time: ? the receiver issues a request for synchronization by asserting the sync~ signal (active low). ? the adc device will detect the sync~ assertion on the fifth rising edge of its local frame clock ( lfc). at the beginning of the frame following detection, each adc transmitter will broadcast a continuous stream of k28.5 symbols in place of data. ? after the receiver has successfully received at least four consecutive k28.5 symbols, it will de-assert the sync~ signal. subclass 0: ? the adc device will detect the de-assertion of the sync~ signal on the rising edge of its device clock, and continue to transmit k28.5 symbols on each lane until the beginning of the frame following detection. ? if the initial lane alignment sequence ( ilas) is not disabled, the adc device will reset its multiframe start marker and transmit an ilas followed by encoded adc data. the ilas will be four multiframes in length. ? if the ilas is disabled, the adc device will begin trans - mitting encoded adc data on each lane. subclass 1: ? the adc device will detect the de-assertion of the sync~ signal on the rising edge of its device clock, and continue to transmit k28.5 symbols on each lane until the beginning of the next multiframe. ? if the ilas is not disabled, the adc device will transmit an ilas at the beginning of the multiframe. the ilas is immediately followed by encoded adc data. ? if the ilas is disabled the adc device will begin trans - mitting encoded adc data on each lane at the beginning of the multiframe boundary. ltc 2123 2123fb
28 for more information www.linear.com/ltc2123 applications information subclass 2: ? unique to this subclass, the sync~ signal must be de-asserted by the receiver on its multiframe bound - ary. the adc device will detect the de-assertion of the sync~ signal on the rising edge of its device clock (for minimum latency error the adc device clock frequency must be greater than or equal to the receiver device clock frequency). ? the adc s local frame clock ( lfc) and local multiframe clock (lmfc) are reset on the detected edge. ? after resetting the internal clocks, the adc device will continue to transmit k28.5 symbols on each lane for one multiframe ( at least 5 frames + 9 octets) to enable the receiver to re-sync to the new clock positions. the adc device will then cease k28.5 transmission at the next multiframe start. ? if the ilas is enabled, the adc device will transmit an ilas followed by encoded adc data. ? if the ilas is not enabled the adc device will transmit encoded adc data on each lane. the start of a code-group will coincide with the start of each k28.5 symbol. the start of a frame will coincide with the first non-k28.5 symbol after the sync~ signal has been de-asserted. initial lane alignment sequence t ransmission (jesd204b 5.3.3.5) when the lane alignment sequence is not disabled via the spi, the sequence illustrated in the lane alignment sequence tables will be transmitted immediately after code-group synchronization is complete. the lane align - ment sequence consists of four complete multiframes. the minimum number of octets in a multiframe is ultimately controlled by the configuration contents of the 2 nd mul - tiframe in the lane alignment sequence. the lane alignment sequence is constructed as follows: ? each multiframe in the sequence will begin with a k28.0 control character, and will end with a k28.3 symbol. ? an 8- bit lane alignment counter is used to generate the octet data for the lane alignment sequence. the counter is reset by the code group synchronization process. the counter is clocked by an octet clock ( character clock). ? the octet of the lane alignment counter is always transmitted during the lane alignment sequence un - less a control character or configuration octet is being transmitted. ? the second multiframe contains the configuration data . the configuration data begins on the 3 rd octet of the multiframe, and is preceded by a k28.4 symbol. ? the lane alignment sequence may not be scrambled ( the scramble option in the spi register is ignored). note that the k28.3 symbol is the lane alignment symbol, and may be used by the receivers to align the multiframe boundary pointers in all the lanes in the link. ltc 2123 2123fb
29 for more information www.linear.com/ltc2123 applications information table 3a. minimum multiframe length ( k=9), 1st multiframe frame description d ata octet (hex) 8b/10b symbol 0 start of subsequence k28.0 octet counter 01 d1.0 1 octet counter 02 d2.0 octet counter 03 d3.0 2 octet counter 04 d4.0 octet counter 05 d5.0 3 octet counter 06 d6.0 octet counter 07 d7.0 4 octet counter 08 d8.0 octet counter 09 d9.0 5 octet counter 0a d10.0 octet counter 0b d11.0 6 octet counter 0c d12.0 octet counter 0d d13.0 7 octet counter 0e d14.0 octet counter 0f d15.0 8 octet counter 10 d16.0 lane alignment symbol k28.3 table 3b. maximum multiframe length ( k=32), 1st multiframe frame description d ata octet (hex) 8b/10b symbol 0 start of subsequence k28.0 octet counter 01 d1.0 1 octet counter 02 d2.0 octet counter 03 d3.0 2 octet counter 04 d4.0 octet counter 05 d5.0 3 octet counter 06 d6.0 octet counter 07 d7.0 4 octet counter 08 d8.0 octet counter 09 d9.0 5 octet counter 0a d10.0 octet counter 0b d11.0 6 octet counter 0c d12.0 octet counter 0d d13.0 7 octet counter 0e d14.0 octet counter 0f d15.0 8 octet counter 10 d16.0 octet counter 11 d17.0 25 octet counter 32 d18.1 octet counter 33 d19.1 26 octet counter 34 d20.1 octet counter 35 d21.1 27 octet counter 36 d22.1 octet counter 37 d23.1 28 octet counter 38 d24.1 octet counter 39 d25.1 29 octet counter 3a d26.1 octet counter 3b d27.1 30 octet counter 3c d28.1 octet counter 3d d29.1 31 octet counter 3e d30.1 lane alignment symbol k28.3 lane alignment sequence tables for tw o lane mode (one lane per adc), 1st multiframe ltc 2123 2123fb
30 for more information www.linear.com/ltc2123 applications information table 3c. minimum multiframe length ( k=9), 2nd multiframe frame description d ata octet (hex) 8b/10b symbol 0 start of subsequence k28.0 start of link configuration k28.4 1 did[7:0] *00 d0.0 {adjcnt[3:0], bid [3:0]} *00 d0.0 2 {0, adjdir, phadj, lid [4:0]} 00 d0.0 {scr, 00, l C1 [4:0]} *01 d1.0 3 f C1 [7:0] 01 d1.0 {000, k C1 [4:0]} *08 d8.0 4 m C1 [7:0] 01 d1.0 {cs[1:0]], 0, [n C1 [4:0]} 4d d13.2 5 {subclassv[2:0], n C1 [4:0]} 0f d15.0 {jesdv[2:0], s C1 [4:0]} 20 d0.1 6 {hd[0], 00, cf[4:0]} 00 d0.0 reserved 00 d0.0 7 reserved 00 d0.0 fchk[7:0] 29 d9.1 8 octet counter 22 d2.1 lane alignment symbol k28.3 table 3d. maximum multiframe length ( k=32), 2nd multiframe frame description d ata octet (hex) 8b/10b symbol 0 start of subsequence k28.0 start of link configuration k28.4 1 did[7:0] *00 d0.0 {adjcnt[3:0], bid [3:0]} *00 d0.0 2 {0, adjdir, phadj, lid [4:0]} *00 d0.0 {scr[0], 00, l C1 [4:0]} *01 d1.0 3 f C1 [7:0] 01 d1.0 {000, k C1 [4:0]} *1f d8.0 4 m C1 [7:0] 01 d1.0 {cs[1:0]], 0, [n C1 [4:0]} 4d d13.2 5 {subclassv[2:0], n C1 [4:0]} 0f d15.0 {jesdv[2:0], s C1 [4:0]} 20 d0.1 6 {hd[0], 00, cf[4:0]} 00 d0.0 reserved 00 d0.0 7 reserved 00 d0.0 fchk[7:0] 40 d0.2 8 octet counter 50 d16.2 octet counter 51 d17.2 25 octet counter 72 d18.3 octet counter 73 d19.3 26 octet counter 74 d20.3 octet counter 75 d21.3 27 octet counter 76 d22.3 octet counter 77 d23.3 28 octet counter 78 d24.3 octet counter 79 d25.3 29 octet counter 7a d26.3 octet counter 7b d27.3 30 octet counter 7c d28.3 octet counter 7d d29.3 31 octet counter 7e d30.3 lane alignment symbol k28.3 lane alignment sequence tables for tw o lane mode (one lane per adc), 2nd multiframe x C1 indicates that field x is affected by -1 encoding {} indicates concatenation * indicates a field directly programmable through the spi configuration field defaults: did=0, bid=0, lid =0, scr=0, l=2, f=2, k =9 or 32, m=2, cs=1, n =14, sub- classv=0, n=16, s=1, hd=0, cf=0 field descriptions: did = device id, bid= bank id, lid= lane id, scr= scrambling enabled, l = lanes per device, f = octets per frame, k =frames per multiframe, m =converters per device, cs =control bits per sample, n =converter resolu- tion, n =total bits per sample, s =samples per converter per frame, hd =high density format, cf =control words per frame per link, fchk=checksum of all fields (mod 256) ltc 2123 2123fb
31 for more information www.linear.com/ltc2123 applications information table 3e. minimum multiframe length ( k=9), 3rd multiframe frame description d ata octet (hex) 8b/10b symbol 0 start of subsequence k28.0 octet counter 25 d5.1 1 octet counter 26 d6.1 octet counter 27 d7.1 2 octet counter 28 d8.1 octet counter 29 d9.1 3 octet counter 2a d10.1 octet counter 2b d11.1 4 octet counter 2c d12.1 octet counter 2d d13.1 5 octet counter 2e d14.1 octet counter 2f d15.1 6 octet counter 30 d16.1 octet counter 31 d17.1 7 octet counter 32 d18.1 octet counter 33 d19.1 8 octet counter 34 d20.1 lane alignment symbol k28.3 table 3f. maximum multiframe length ( k=32), 3rd multiframe frame description d ata octet (hex) 8b/10b symbol 0 start of subsequence k28.0 octet counter 81 d1.4 1 octet counter 82 d2.4 octet counter 83 d3.4 2 octet counter 84 d4.4 octet counter 85 d5.4 3 octet counter 86 d6.4 octet counter 87 d7.4 4 octet counter 88 d8.4 octet counter 89 d9.4 5 octet counter 8a d10.4 octet counter 8b d11.4 6 octet counter 8c d12.4 octet counter 8d d13.4 7 octet counter 8e d14.4 octet counter 8f d15.4 8 octet counter 90 d16.4 octet counter 91 d17.4 25 octet counter b2 d18.5 octet counter b3 d19.5 26 octet counter b4 d20.5 octet counter b5 d21.5 27 octet counter b6 d22.5 octet counter b7 d23.5 28 octet counter b8 d24.5 octet counter b9 d25.5 29 octet counter ba d26.5 octet counter bb d27.5 30 octet counter bc d28.5 octet counter bd d29.5 31 octet counter be d30.5 lane alignment symbol k28.3 lane alignment sequence tables for tw o lane mode (one lane per adc), 3rd multiframe ltc 2123 2123fb
32 for more information www.linear.com/ltc2123 applications information table 3g. minimum multiframe length ( k=9), 4th multiframe frame description d ata octet (hex) 8b/10b symbol 0 start of subsequence k28.0 octet counter 37 d23.1 1 octet counter 38 d24.1 octet counter 39 d25.1 2 octet counter 3a d26.1 octet counter 3b d27.1 3 octet counter 3c d28.1 octet counter 3d d29.1 4 octet counter 3e d30.1 octet counter 3f d31.1 5 octet counter 40 d0.2 octet counter 41 d1.2 6 octet counter 42 d2.2 octet counter 43 d3.2 7 octet counter 44 d4.2 octet counter 45 d5.2 8 octet counter 46 d6.2 lane alignment symbol k28.3 table 3h. maximum multiframe length ( k=32), 4th multiframe frame description d ata octet (hex) 8b/10b symbol 0 start of subsequence k28.0 octet counter c1 d1.6 1 octet counter c2 d2.6 octet counter c3 d3.6 2 octet counter c4 d4.6 octet counter c5 d5.6 3 octet counter c6 d6.6 octet counter c7 d7.6 4 octet counter c8 d8.6 octet counter c9 d9.6 5 octet counter ca d10.6 octet counter cb d11.6 6 octet counter cc d12.6 octet counter cd d13.6 7 octet counter ce d14.6 octet counter cf d15.6 8 octet counter d0 d16.6 octet counter d1 d17.6 25 octet counter f2 d18.7 octet counter f3 d19.7 26 octet counter f4 d20.7 octet counter f5 d21.7 27 octet counter f6 d22.7 octet counter f7 d23.7 28 octet counter f8 d24.7 octet counter f9 d25.7 29 octet counter fa d26.7 octet counter fb d27.7 30 octet counter fc d28.7 octet counter fd d29.7 31 octet counter fe d30.7 lane alignment symbol k28.3 lane alignment sequence tables for tw o lane mode (one lane per adc), 4th multiframe ltc 2123 2123fb
33 for more information www.linear.com/ltc2123 applications information jesd204b modes of operation scramble mode (jesd204b 5.2, annex d) to avoid spectral interference from the serial data output, a spi enabled data scrambler is added between the adc data and the 8 b/10b encoder to randomize the spectrum of the serial link. the polynomial used for the scrambler is 1+x 14 +x 15 , which is a pseudorandom pattern repeating itself every 2 15 C1. the scrambled data is converted into two valid 8b/10b code-groups. the 8 b/10b code-groups are then serialized and transmitted. the receiver is required to deserialize the data, decode the code-groups into octets, and descramble them back to the original octets using the self-aligning descrambler described in jesd204b 5.2. frame alignment monitoring ( fam ) (jesd204b 5.3.3.4, 7.3) a frame contains more than one octet or code-group, so it is necessary to periodically verify that the frame alignment of the receiver is correct. when frame alignment monitoring is not disabled via the spi, the receiver may verify frame alignment without the loss of data. to accomplish this, predetermined data in the last code-group of the frame is substituted with the control character, k28.7. the receiver is required to detect the k 28.7 character and replace it with the original data . in this way, the last octet or code-group may be verified . there are two possible frame alignment monitoring modes. fam mode 1 is implemented when scrambling is not enabled as follows: ? if the data in the last code-group of the current frame equals the data in the last code-group of the previous frame, the converter will replace the last code-group with the control character k28.7 before serialization . however, if a k28.7 symbol was already transmitted in the previous frame, the actual code-group will be transmitted. if lane alignment monitoring is enabled and it is the last code-group of a multiframe, a k28.3 will be transmitted in place of the k28.7, even if a control character was transmitted in the previous frame. ? upon receiving a k28.7 symbol, the receiver is required to replace it with the data decoded at the same position of the previous frame. fam mode 2 is implemented when scrambling is enabled as follows: ? if the data in the last code-group of the current frame equals d28.7, the converter will replace this data with the k 28.7 control character. if lane alignment monitoring is enabled and it is the last code-group of a multiframe, a k28.3 will be transmitted in place of the k28.7. ? upon receiving a k28.7 symbol, the receiver is required to replace it with d28.7. with fam enabled the receiver is required to search for the presence of k28.7 symbols in the data stream. if two successive k28.7 symbols are detected at the same posi - tion other than the assumed end of frame, the receiver will realign its frame boundar y to the new position. lane alignment monitoring (lam) (jesd204b 5.3.3.6, 7.5) when multiple lanes are present in a link, it is useful to periodically monitor the continued alignment of each lane. ltc 2123 2123fb
34 for more information www.linear.com/ltc2123 applications information lane alignment symbols are inserted into the transmitted data on a substitution basis to enable the receiver to verify lane alignment without the loss of data. in this mode, pre - determined data in the last code group of a multiframe is substituted with the control character k28.3. the receiver is required to detect the k28.3 character and replace it with the original data. in this way, the last code group of a multiframe may be marked and used for lane alignment . there are two possible lane alignment monitoring modes . lam mode 1 is implemented when scrambling is not enabled as follows: ? if it is the last code group of a multiframe and the data equals the data in the last code group of the previous frame, the converter will replace the current code group with the control character k28.3. ? upon receiving a k28.3 symbol, the receiver is required to replace it with the data decoded at the same position of the previous frame. lam mode 2 is implemented when scrambling is enabled as follows: ? if it is the last code group of a multiframe and the data of code group equals d28.3, the converter will replace this data with the k28.3 control character. ? upon receiving a k28.3 symbol, the receiver is required to replace it with d28.3. simple and complex periodic test patterns seven test patterns are a provided to the user for evalua - tion and system debug. pattern 1: periodic k28.5 pattern 1 contains both disparities of the k28.5 comma, and is 20 bits long. the k28.5 pattern contains a unique combination of maximum and minimum run-lengths, making this pattern useful in quickly observing the effects of inter symbol interference (isi). pattern 2: periodic k28.7 pattern 2 produces a square wave of the minimum pos - sible frequency for the high speed serial interface (a 1111100000 pattern). pattern 3: periodic d21.5 pattern 3 produces the maximum possible frequency for the high speed interface (a 1010 pattern). pattern 4: prbs15 pattern 4 is a pseudo random bit sequence based on the polynomial 1+x 14 +x 15 ( the same polynomial used by the scrambler described in jesd204b 5.2). when this pattern is selected, the scrambler is internally forced on and the adc data is forced to zero. the length of the sequence is 2 15 C1 prior to 8b/10b encoding. when frame and lane alignment monitoring are not disabled, substitution of data will take place as described in the frame alignment monitoring and lane alignment sections of this data sheet. pattern 5: repeated lane alignment sequence pattern 5 is the continuous transmission of the lane align- ment sequence as described in jesd204b 5.3.3.8.2. in this mode, the following occurs: case 1 - sync~ is active before entering this state ? code group synchronization is performed ( k28.5 com - mas are transmitted in whole frames until sync~ is de-asserted). ? the lane alignment sequence is transmitted repeatedly according to tables 3a to 3h. case 2 - sync~ is not active before entering this state ? at least one multiframe of k28.5 commas are transmit - ted. ? the lane alignment sequence is transmitted repeatedly according to tables 3a to 3h. if scrambling is enabled, the test samples will not be scrambled. this test sequence is sensitive to a synchronization request from the receiver. if the sync~ signal is asserted at any time during test sample transmission, the lane alignment sequence pointer will be reset, and case 1 will be repeated. ltc 2123 2123fb
35 for more information www.linear.com/ltc2123 pattern 6: test sample sequence pattern 6 is a set of test samples defined in jesd204b 5.1.6.3. the transmission of these test samples over the link provides a way to verify that the data mapping of the adc matches the receiver. to place the adc in the test sample transmission mode, the corresponding bit must be set in the periodic test pattern spi register. once this bit is set, the following occurs: case 1 - sync~ is active before entering this state ? code-group synchronization is performed ( k28.5 com - mas are transmitted in whole frames until sync~ is de-asserted). ? the lane alignment sequence is transmitted ( if enabled) according to tables 3a to 3h. ? the test samples are repeatedly transmitted according to tables 4a to 4b. applications information case 2 - sync~ is not active before entering this state ? four k28.5 commas are transmitted. ? the lane alignment sequence is transmitted ( if enabled) according to tables 3a to 3h. ? the test samples are repeatedly transmitted according to tables 4a to 4b. if scrambling is enabled, the test samples will be scrambled , but the lane alignment sequence will not be scrambled. this test sequence is sensitive to a synchronization request from the receiver. if the sync~ signal is asserted at any time during test sample transmission, the test sample sequence pointer will be reset, and case 1 will be repeated. table 4 a . pattern 6 test sample data description for 1 lane/ adc ( l =2), 2 octets per frame ( f =2),1 sample / converter/ frame period ( s =1) test sample sequence adc 0 adc 1 lane 0 octets lane 1 octets frame 0 (cid+1) 0000_0000 0000_011 0 0000_0000 0000_1000 frame 1 (sid+1) 0000_0000 0000_0100 0000_0000 0000_011 0 frame i, 2ik (msb set to 1) 1000_ 0000 0000_0000 1000_0000 0000_0000 table 4 b . pattern 6 test sample data description for 2 lanes/ adc, (l =4), 2 octets per frame ( f =2), 2 samples/ converter/ frame period ( s =2) test sample sequence adc 0 adc 1 lane 0 octets lane 1 octets lane 2 octets lane 3 octets frame 0 (cid +1) 0000_0000 0000_01 1 0 0000_0000 0000_0100 0000_0000 0000_1000 0000_0000 0000_1000 frame 1 (sid +1) 0000_0000 0000_0100 0000_0000 0000_10 1 0 0000_0000 0000_0100 0000_0000 0000_1000 frame 2 1000_0000 0000_0000 1000_0000 0000_0000 1000_0000 0000_00 1 0 1000_0000 0000_0000 frame 3 1000_0000 0000_0000 1000_0000 0000_0000 1000_0000 0000_0000 1000_0000 0000_001 0 frame i, 2ik (msb set to 1) 1000_ 0000 0000_0000 1000_0000 0000_0000 1000_0000 0000_0000 1000_0000 0000_0000 note: cid = converter id, sid=sample id, k =frames in multiframe, 1 indicates the control-bit position (overflow bit) ltc 2123 2123fb
36 for more information www.linear.com/ltc2123 applications information pattern 7: modified r pat jesd204b clauses 4.4.1, 4.5.1 and 4.6.1 require that one of two possible patterns be supported by the transmitter for jitter compliance testing. the modified rpat pattern is one of these two patterns, and consists of 12 specific code-groups repeated continuously (a description of the modified rpat sequence may be found in ieee std . 802.3- 2008 annex 48a). this rpat pattern must begin with positive disparity. to gracefully force positive disparity, a ten character preamble is transmitted. the first nine characters will be the d5.6 code-group. the d5.6 preserves the previous disparity. if the disparity of these nine symbols is positive, the tenth preamble character will also be a d5.6 symbol. if the disparity is negative a reversal is forced by transmitting a d16.2 code-group as the tenth preamble character. serial programming the cs , sck, sdi and sdo pins make up the serial pe - ripheral inter face ( spi) that programs the a/d control registers. data is written to a register with a 16- bit serial word. data can also be read back from a register to verify its contents. serial data transfer starts when cs is taken low. the data on the sdi pin is latched at the first sixteen rising edges of sck. any sck rising edges after the first sixteen are ignored. the data transfer ends when cs is taken high again. the first bit of the 16- bit input word is the r/ w bit. the next seven bits are the address of the register ( a6:a0). the final eight bits are the register data (d7:d0). if the r/ w bit is low, the serial data ( d7:d0) will be written to the register set by the address bits (a6:a0). if the r/ w bit is high, data in the register set by the ad - dress bits (a6:a0) will be read back on the sdo pin (see the timing diagrams). during a readback command the register is not updated and data on sdi is ignored. the sdo pin is an open-drain output that pulls to ground with a 200 impedance. if register data is read back through sdo, an external 2 k pull-up resistor is required. if serial data is only written and readback is not needed, then sdo can be left floating and no pull-up resistor is needed. table 6 shows a map of the mode control registers. soft reset the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. a global reset of all spi registers to the default values may be performed by writing a 1 to bit d7 of address 0. after the reset is complete, bit d7 is automatically set back to zero. this register is write-only. table 5. modified r pat test pattern code group name octet value (hex) disparity d30.5 be + d23.6 d7 C d3.1 23 + d7.2 47 + d11.3 6b + d15.4 8f + d19.5 b3 + d20.0 14 + d30.2 5e C d27.7 fb + d21.1 35 + d25.2 59 + ltc 2123 2123fb
37 for more information www.linear.com/ltc2123 applications information table 6. spi register memory map spi register description address d7 d6 d5 d4 d3 d2 d1 d0 soft reset 0 reset power down 1 sleep nap pdb pda adc cntl 2 2x_clk of_en dcs_en device id 3 did[7:0] bank id 4 bid[3:0] lanes (C1) 5 l C1 [2:0] frames/multiframe (C1) 6 k C1 [4:0] jesd204b modes 7 las_dis lam_dis fam_dis reserved rst_dis scr_en jesd204b subclass modes 8 r C1 [2:0] (alert length) alert tx_sync subclass[2:0] periodic test patterns 9 pat [2:0] normal data 0 0 0 k28.5 (sync comma) 0 0 1 k28.7 (1111100000) 0 1 0 d21.5 (10101010) 0 1 1 prbs15 (1+x 14 +x 15 ) 1 0 0 lane alignment sequence 1 0 1 test samples sequence 1 1 0 modified rpat pattern 1 1 1 cml output magnitude 10 cml bias[1:0] 10ma (250mv) 0 0 12ma (300mv) 0 1 14ma (350mv) 1 0 16ma (400mv) 1 1 note: x C1 indicates that field x is affected by C1 encoding ltc 2123 2123fb
38 for more information www.linear.com/ltc2123 applications information register a0: reset register (address 00h) d7 d6 d5 d4 d3 d2 d1 d0 reset x x x x x x x this register is "write only. readback from this register will be all ones bit 7 reset software reset bit 0 = reset disabled 1 = software reset. all spi registers are set to default values. this bit is automatically set back to zero after the reset is complete. bits 6-0 unused bits register a1: power down modes (address 01h) d7 d6 d5 d4 d3 d2 d1 d0 x x x x sleep nap pdb pda bits 7-4 unused bit bit 3 sleep 0 = normal operation 1 = power down entire adc bit 2 nap 0 = normal operation (default setting) 1 = low power keep-alive mode for both channels bit 1 pdb 0 = normal operation (default setting) 1 = power down channel b bit 0 pda 0 = normal operation (default setting) 1 = power down channel a register a2: adc control (address 02h) d7 d6 d5 d4 d3 d2 d1 d0 x x x x x 2x_clk of_en dcs_en bits 7-3 unused bits bit 2 2x_clk 0 = devclk frequency is equal to sample frequency (default setting) 1 = devclk frequency is t wice the sample frequency bit 1 of_en 0 = lvds overflow output is disabled (default setting) 1 = l vds overflow output is enabled bit 0 dcs_en 0 = duty cycle stabilizer is disabled (default setting) 1 = duty cycle stabilizer is enabled register a3: device id (address 03h) d7-d0 did[7:0] bits 7-0 did[7:0] device id. default value is 00000000 did is defined in jesd204b 8.3. it is only used during the transmission of an initial lane alignment sequence and does not impact the configuration or functionality of the adc ltc 2123 2123fb
39 for more information www.linear.com/ltc2123 applications information register a4: bank id (address 04h) d7 d6 d5 d4 d3-d0 x x x x bid[3:0] bits 7-4 unused bits bits 3-0 bid[3:0] bank id. default value is 0000 bid is defined in jeds204b 8.3. provided as an extension to the did word. it is only used during the transmission of an initial lane alignment sequence, and does not impact the configuration or functionality of the adc or serial link register a5: number of lanes C1 (address 05h) d7 d6 d5 d4 d3 d2-d0 x x x x x l C1 [2:0] bits 7-3 unused bits bits 2-0 lC1[2:0] the value of l configures the device. it is also transmitted in the lane alignment sequence 001 = 2 lanes (one lane per adc, default setting) 011 = 4 lanes ( tw o lanes per adc) register a6: number of frames per multiframe C1 (address 06h) d7 d6 d5 d4-d0 x x x k C1 [4:0] bits 7-5 unused bits bits 4-0 k C1 [4:0] frames per multiframe minus 1. default value is 01111 (16 frames per multiframe) k is defined in jeds204b 5.3.3.5. for both two and four lane operation, the minimum valid value of k is 9 (k C1 = 01000) and the maximum valid value is 32 (k C1 = 11111) register a7: jesd204b modes (address 07h) d7 d6 d5 d4 d3 d2 d1 d0 x x las_dis lam_dis fam_dis 0 rst_dis scr_en bits 7-6 unused bits bit 5 las_dis 0 = lane alignment sequence enabled (default setting) 1 = lane alignment sequence disabled bit 4 lam_dis 0 = lane alignment monitor enabled (default setting) 1 = lane alignment monitor disabled bit 3 fam_dis 0 = frame alignment monitor enabled (default setting) 1 = frame alignment monitor disabled bit 2 reserved bit. set to 0 bit 1 rst_dis 0 = in subclass 1, sysref reset of dividers is enabled (default setting) in subclass 2 sync~ reset of dividers is enabled (default setting) 1 = in subclass 1, sysref reset of dividers is disabled in subclass 2 sync~ reset of dividers is disabled bit 0 scr_en 0 = scrambling is disabled (default setting) 1 = scrambling is enabled ltc 2123 2123fb
40 for more information www.linear.com/ltc2123 applications information register a8: jesd204b subclass modes (address 08h) d7-d5 d4 d3 d2-d0 r C1 [2:0] alert tx_sync subclassv[2:0] bits 7-5 r C1 [2:0] subclass 1 alert mode de-arming length. default value is 000 (r = 1). measured in multiframe periods bit 4 alert subclass 1 alert mode. first pulse arms, second pulse (and later) are active 0 = alert mode disabled (default setting) 1 = alert mode enabled bit 3 tx_sync a multiframe of k28.5 commas are transmitted if multiframe position changes 0 = transmitter induced synchronization disabled (default setting) 1 = transmitter induced synchronization enabled bits 2-0 subclassv[2:0] 000 = jesd204b subclass 0 (default setting) 001 = jesd204b subclass 1 (deterministic latency obtained using sysysref) 010 = jesd204b subclass 2 (deterministic latency obtained using sync~ rising edge) register a9: periodic test patterns (address 09h) d7 d6 d5 d4 d3 d2-d0 x x x x x pat [2:0] bits 7-3 unused bits bits 2-0 pat [2:0] 000 = normal adc data 001 = k28.5 pattern (sync comma) 010 = k28.7 pattern (1111100000) 011 = d21.5 pattern (1010101010) 100 = prbs15 pattern (1+x 14 +x 15 ) 101 = lane alignment sequence 110 = test samples sequence 111 = modified rpat pattern register a10: cml output magnitude (address 0ah) d7 d6 d5 d4 d3 d2 d1-d0 x x x x x x cmlbias[1:0] bits 7-2 unused bits bits 1-0 cmlbias[1:0] affects all cml outputs 00 = 10ma (250mv) 01 = 12ma (300mv) 10 = 14ma (350mv) 11 = 16ma (400mv) ltc 2123 2123fb
41 for more information www.linear.com/ltc2123 applications information high speed cml output terminations the cml outputs must be terminated in the transmission line characteristic impedance for proper functionality . in general, the transmission line impedance should be designed to provide either 50 single-ended or 100 differential. the ov dd supply voltage and the termination voltage determine the common mode output level of the cml outputs. for proper operation of the cml driver, the output common mode voltage should be greater than 1v. the directly-coupled termination mode of figure 15 is recommended when the receiver termination voltage is within the required range. when the cml outputs are directly-coupled to the 50 termination resistors, the ov dd supply voltage also serves as the receiver termina- tion voltage , and the output common mode voltage will be in the range of 125 mv to 200 mv lower than ov dd (depending on the programmed cml current). in this mode the ov dd voltage should be in the range of 1.125v to 1.2v (minimum), and v dd (maximum). the directly-coupled differential termination of figure 16 may be used when no termination voltage at the receiver is available as long as the input common mode voltage is within the required range. in this case, the common mode voltage will be in the range of 250 mv to 400mv below ov dd . the minimum ov dd should be in the range of 1.25 v to 1.4v ( depending on the programmed cml current). the maximum ov dd is equal to v dd . if the serial receivers common mode input requirements are not compatible with the directly-coupled termination modes, the dc balanced 8 b/10b encoded data will permit dc blocking capacitors as shown in figure 17. in this ac-coupled mode, the termination voltage is determined by the receivers requirements. the coupling capacitors should be selected appropriately for the intended operating bit-rate, usually between 1nf to 10nf. in the ac-coupled mode, the output common mode voltage will be 250 mv to 400mv below ov dd , so the ov dd supply voltage should be in the same range as the directly coupled differential case . the ltc2123 is fully ac compliant with the jesd204b specification. table 7. minimum ov dd voltage cml current directl y coupled min ov dd directly coupled differential min ov dd ac coupled min ov dd 10ma 1.125v 1.25v 1.25v 12ma 1.15v 1.3v 1.3v 14ma 1.175v 1.35v 1.35v 16ma 1.2v 1.4v 1.4v ltc 2123 2123fb
42 for more information www.linear.com/ltc2123 applications information serial cml driver serial cml receiver 2123 f14 1.2v to v dd (16ma bias) cmlout + data + data ? gnd spi programmable 10ma to 16ma 50 50 50 50 cmlout ? ov dd z o z o serial cml driver serial cml receiver 2123 f15 1.4v to v dd (16ma bias) cmlout + data + data ? gnd spi programmable 10ma to 16ma 50 50 100 cmlout ? ov dd z o z o figure 15. cml termination, directly coupled mode figure 16. cml termination, directly coupled differential mode ltc 2123 2123fb
43 for more information www.linear.com/ltc2123 applications information serial cml driver serial cml receiver 2123 f16 1.4v to v dd (16ma bias) vterm cmlout + data + data ? gnd spi programmable 10ma to 16ma 50 50 50 0.01f 0.01f 50 cmlout ? ov dd z o z o figure 17. cml termination, ac-coupled mode grounding and bypassing the ltc2123 requires a printed circuit board with a clean unbroken ground plane in the first layer beneath the adc. a multilayer board with an internal ground plane is rec - ommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , v ref pins. bypass capacitors must be located as close to the pins as possible. size 0402 ceramic capacitors are rec - ommended. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the analog inputs, clock signals, and digital outputs should not be routed next to each other. ground fill and grounded vias should be used as barriers to isolate these signals from each other. heat transfer most of the heat generated by the ltc2123 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the pc board. this pad should be connected to the internal ground planes by an array of vias. ltc 2123 2123fb
44 for more information www.linear.com/ltc2123 typical applications silkscreen top ltc 2123 2123fb
45 for more information www.linear.com/ltc2123 typical applications top side inner layer 2, gnd ltc 2123 2123fb
46 for more information www.linear.com/ltc2123 typical applications inner layer 3 inner layer 4 ltc 2123 2123fb
47 for more information www.linear.com/ltc2123 typical applications inner layer 5, gnd bottom layer ltc 2123 2123fb
48 for more information www.linear.com/ltc2123 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 7.00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (wkkd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 chamfer c = 0.35 0.40 0.10 4847 1 2 bottom view?exposed pad 5.50 ref (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uk48) qfn 0406 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 5.50 ref (4 sides) 6.10 0.05 7.50 0.05 0.25 0.05 0.50 bsc package outline 5.15 0.10 5.15 0.10 5.15 0.05 5.15 0.05 r = 0.10 typ uk package 48-lead plastic qfn (7mm 7mm) (reference ltc dwg # 05-08-1704 rev c) ltc 2123 2123fb
49 for more information www.linear.com/ltc2123 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 09/14 updated the maximum specification for p diss updated the typical application 4 50 b 11/14 updated the crosstalk specification added t dck specification updated the t su_sys and t h_sys specifications 3 5 6 ltc 2123 2123fb
50 for more information www.linear.com/ltc2123 ? linear technology corporation 2014 lt 1114 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2123 related parts typical application part number description comments high speed adcs ltc2122 14-bit, 170msps 1.8v dual adc, jesd204b serial outputs 781mw, 70db snr, 90db sfdr, 7mm 7mm qfn package, 6.2gbps (single lane) serial interface ltc2158-14 14-bit, 310msps 1.8v dual adc, ddr lvds outputs 724mw, 68.8db snr, 88db sfdr, 9mm 9mm qfn package ltc2157-14/ ltc2156-14/ ltc2155-14 14-bit, 250msps/210msps/170msps, 1.8v dual adc, ddr lvds outputs 650mw/616mw/567mw, 70db snr, 90db sfdr, 9mm 9mm qfn package ltc2274 16-bit 105msps 3.3v single adc with jesd204 serial outputs 1300mw, 77.6db snr, 100db sfdr, 6mm 6mm qfn package receiver subsystems lt m ? 9013 300mhz wideband receiver integrated i/q demodulator, if amplifier, and dual 14-bit, 310msps high speed adc, 15mm 15mm bga package 2123 ta02 ltc2123 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 v dd gnd a ina + a ina ? sense v ref v cm gnd a inb ? a inb + gnd v dd 13 14 15 16 17 18 19 20 21 22 23 24 v dd gnd devclk ? devclk + gnd sysref + sysref ? gnd sync~ + sync~ ? v dd v dd 49 48 47 46 45 44 43 42 41 40 39 38 37 gnd v dd gnd cs sck sdi sdo of + of ? gnd gnd v dd v dd ov dd ov dd cmlout_a1 + cmlout_a1 ? cmlout_a0 + cmlout_a0 ? cmlout_b0 + cmlout_b0 ? cmlout_b1 + cmlout_b1 ? ov dd ov dd r18 0 r14 100 sync~ ? cmlout_a1+ cmlout_a1? cmlout_a0+ cmlout_a0? cmlout_b0+ cmlout_b0? cmlout_b1+ cmlout_b1? cs sck sdi sdo of+ of? sync~ + sysref ? sysref + r15 0 r5 1k v dd c11 2.2f c25 2.2f r15 0 r17 100 r6 45.3 r62 4.99 r63 4.99 r8 24.9 r9 24.9 r7 45.3 c24 0.1f aina c22 0.1f t1 maba-007159-000000 r66 100 r10 45.3 r64 4.99 r65 4.99 r11 45.3 c29 0.1f r67 100 c26 2.2f ? ? c23 0.1f 5 4 1 3 ainb c27 0.1f t2 maba-007159-000000 ? ? c28 0.1f 5 4 1 3 r13 0 r12 0 devclk ? devclk + c42?c49 1000pf high speed cmlout traces are 50 c20 0.1f ov dd ov dd ov dd v dd v dd v dd v dd c21 0.1f c12 0.1f v dd c13 0.1f c14 0.1f c15 0.1f c16 0.1f c17 0.1f c18 0.1f c19 0.1f v dd aina + aina ? ainb ? ainb + ltc 2123 2123fb

▲Up To Search▲

Price & Availability of LTC2123-15

	To Download LTC2123-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .